The 4033 and 4034 are high performance programmable pulse generators for testing digital systems and circuits based on TTL, CMOS, or ECL technologies. These instruments generate clean and accurate pulses at up to 6 digits resolution with a repetition rate up to 50 MHz, variable pulse widths from 10 ns to 10 s, and pulse delays from 0 ns to 10 s.
![Pulse Pulse](/uploads/1/2/5/8/125870749/120127253.jpg)
DG645 Specifications | |
Delays | |
Channels | 4 independent pulses controlled in position and width. 8 delay channels available as an option (see Output Options below) |
Range | 0 to 2000 seconds |
Resolution | 5 ps |
Accuracy | 1 ns + (timebase error × delay) |
Jitter (rms) Ext. trig. to any output T0 to any output | 25 ps + (timebase jitter × delay) 15 ps + (timebase jitter × delay) |
Trigger delay | 85 ns (ext. trigger to T0 output) |
Timebases | |
Standard crystal | |
Jitter | 10-8 s/s |
Stability | 2 x 10-6 (20 °C to 30 °C) |
Aging | 5 ppm/yr |
Opt. 4 OCXO | |
Jitter | 10-11 s/s |
Stability | 2 x 10-9 (20 °C to 30 °C) |
Aging | 0.2 ppm/yr |
Opt. 5 Rubidium | |
Jitter | 10-11 s/s |
Stability | 2 x 10-10 (20 °C to 30 °C) |
Aging | 0.0005 ppm/yr |
External input | 10 MHz ± 10 ppm, sine >0.5 Vpp, 1 kΩ impedance |
Output | 10 MHz, 2 Vpp ine into 50 Ω |
External Trigger | |
Rate | DC to 1/(100 ns + longest delay). Maximum of 10 MHz |
Threshold | ±3.50 VDC |
Slope | Trigger on rising or falling edge |
Impedance | 1 MΩ + 15 pF |
Internal Rate Generator | |
Trigger modes | Continuous, line or single shot |
Rate | 100 µHz to 10 MHz |
Resolution | 1 µHz |
Accuracy | Same as timebase |
Jitter (rms) | <25 ps (10 MHz/N trigger rate) <100 ps (other trigger rates) |
Burst Generator | |
Trigger to first T0 Range Resolution | 0 to 2000 s 5 ps |
Period between pulses Range Resolution | 100 ns to 42.9 s 10 ns |
Delay cycles per burst | 1 to 232 - 1 |
Outputs (T0, AB, CD, EF and GH) | |
Source impedance | 50 Ω |
Transition time | <2 ns |
Overshoot | <100 mV + 10 % of pulse amplitude |
Offset | ±2 V |
Amplitude | 0.5 to 5.0 V (level + offset <6.0 V) |
Accuracy | 100 mV + 5 % of pulse amplitude |
General | |
Computer interfaces | GPIB (IEEE-488.2), RS-232 and Ethernet. All instrument functions can be controlled through the interfaces. |
Non-volatile memory | Nine sets of instrument configurations can be stored and recalled. |
Power | <100 W, 90 to 264 VAC, 47 Hz to 63 Hz |
Dimensions | 8.5' × 3.5' × 13' (WHL) |
Weight | 9 lbs. |
Warranty | One year parts and labor on defects in materials & workmanship |
Output Options | |
Option 1 (delay outputs) | |
Number of outputs | 8 (rear-panel BNCs) |
Outputs | T0, A, B, C, D, E, F, G and H |
Source impedance | 50 Ω |
Transition time | <1 ns |
Overshoot | <100 mV |
Level | +5 V CMOS logic |
Pulse characteristics Rising edge Falling edge | At programmed delay 25 ns after longest delay |
Option 2 (high-voltage outputs) | |
Number of outputs | 8 (rear-panel BNCs) |
Outputs | T0, A, B, C, D, E, F, G and H |
Source impedance | 50 Ω |
Transition time | <5 ns |
Levels | 0 to 30 V into high impedance, 0 to 15 V into 50 Ω (amplitude decreases by 1 %/kHz) |
Pulse characteristics Rising edge Falling edge | At programmed delay 100 ns after the rising edge |
Option 3 (combinatorial outputs) | |
Number of outputs | 8 (rear-panel BNCs) |
Outputs | T0, AB, CD, EF, GH, (AB+CD), (EF+GH), (AB+CD+EF), (AB+CD+EF+GH) |
Source impedance | 50 Ω |
Transition time | <1 ns |
Overshoot | <100 mV + 10 % of pulse amplitude |
Pulse characteristics T0, AB, CD, EF, GH (AB+CD), (EF+GH) (AB+CD+EF) (AB+CD+EF+GH) | Logic high for time between delays Two pulses created by the logic OR of the given channels Three pulses created by the logic OR of the given channels Four pulses created by the logic OR of the given channels |
Option SRD1 (fast rise time module) | |
Rise time | <100 ps |
Fall time | <3 ns |
Offset | -0.8 V to -1.1 V |
Amplitude | 0.5 V to 5.0 V |
Load | 50 Ω |